Circuit architecture for I/Q mismatch mitigation in direct conversion receivers

ABSTRACT

An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

FIELD OF THE DISCLOSURE

This disclosure relates in general to the field of electronic devicesand, more particularly, to circuit architecture for I/Q mismatchmitigation in direct conversion receivers.

BACKGROUND

A direct-conversion receiver (DCR), also called a homodyne receiver,demodulates incoming radio frequency signals using synchronous detectiondriven by a local oscillator. DCRs are applied in many electronicdevices, including cellphones televisions, avionics, medical imagingapparatus, and software-defined radio systems. Complexity, cost, powerdissipation, and number of external components have been some of thecriteria in selecting receiver architectures for today's digitalcommunications market. Of the many alternatives, DCR has emerged as thearchitecture of choice to best meet these requirements. However, the DCRarchitecture involves some design challenges including direct current(DC) offset, In-Phase/Quadrature phase (I/Q) mismatch, and even-orderdistortion, which can affect the DCR's performance if not managedproperly.

SUMMARY OF THE DISCLOSURE

An example electrical circuit is provided and includes a localoscillator configured to generate a first reference signal and a secondreference signal having a predetermined phase shift with the firstreference signal, an I-channel mixer configured to inject the firstreference signal to an incoming signal and generate a first output, acompensation mixer configured to multiply the first output with aconstant factor to generate a second output, a first low pass filterconfigured to approximately attenuate frequencies in the second outputto generate a third output, and a first correcting filter configured tofilter the third output to generate a fourth output. The firstcorrecting filter is configured to reduce a channel impulse responsemismatch between the first low pass filter and a second low pass filter,which is configured to attenuate frequencies in a Q-channel of theincoming signal. In specific embodiments, the phase shift includes 45°,and the constant factor is two over square root of two.

As used herein, the term “local oscillator” includes an electronicoscillator that can generate a repetitive, oscillating electronicalternating current signal, for example, a sine wave or a square wave.The local oscillator can comprise any suitable architecture, includingcrystal oscillator, voltage controlled oscillator, feedback oscillator,etc. The term “mixer” includes an electronic circuit configured tomultiply two input signals to generate a third output signal. As usedherein, the term “low pass filter” includes a suitably configuredelectronic circuit configured to pass low frequency signals (below apreconfigured threshold frequency) and attenuate signals withfrequencies higher than the threshold frequency. An example low passfilter comprises a resistor in series with a load and a capacitor inparallel with the load.

In specific embodiments, the electrical circuit further includes aQ-channel mixer configured to inject the second reference signal to theincoming signal to generate a fifth output, where the second low passfilter is configured to approximately attenuate frequencies in the fifthoutput to generate a sixth output, a second correcting filter configuredto filter the sixth output to generate a seventh output, where thesecond correcting filter is configured to reduce the channel impulseresponse mismatch between the first low pass filter and the second lowpass filter, an alpha mixer configured to inject a gain correction tothe seventh output to generate an eighth output, and a gain correctionadder configured to add the eighth output with the fourth output togenerate a ninth output.

In specific embodiments, the I-channel mixer, the Q-channel mixer, andthe compensation mixer are in an analog domain, and the first low passfilter, the second low pass filter, the first correcting filter, thesecond correcting filter, the alpha mixer, and the gain correction adderare in a digital domain. In some embodiments, a first set of filtercoefficients of the first correcting filter, a second set of filtercoefficients of the second correcting filter and the gain correction aredetermined by minimizing a predetermined cost function, which can be afunction of the power of the incoming signal. In some embodiments, thecost function may be processed by a digital signal processor.

BRIEF DESCRIPTION OF THE DRAWINGS

To provide a more complete understanding of the present disclosure andfeatures and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying figures, whereinlike reference numerals represent like parts, in which:

FIG. 1 is a simplified circuit diagram of a circuit architecture for I/Qmismatch mitigation in direct conversion receivers in accordance withone embodiment;

FIG. 2 is a simplified diagram illustrating another embodiment of thecircuit architecture; and

FIG. 3 is a simplified diagram illustrating yet another embodiment ofthe circuit architecture.

DETAILED DESCRIPTION

The present disclosure provides for DCR circuit architecture that cancompensate for IQ mismatches. Ideal (theoretical) DCRs translate afrequency band of interest in the incoming signal to zero frequency andemploy low pass filters (LPFs) to suppress nearby interferers. Inpractice, however, analog implementations of DCRs generally suffer fromI/Q imbalances due to gain and phase errors generated by components ofthe LPFs and the local oscillators in the I/Q paths. As a result, theperformance of the DCRs and the quality of the received signal can bedegraded.

For example, assuming an incoming signal (s) at the DCR having in-phase(I-channel) and quadrature phase (Q-channel) components as follows:

$\begin{matrix}{s = {{\left\lbrack {\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}}} \right\rbrack{\cos\left( {\omega_{c}t} \right)}} + {\left\lbrack {\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}}} \right\rbrack{\sin\left( {\omega_{c}t} \right)}}}} & (1)\end{matrix}$

where ω_(c) is the frequency of the signal, a_(n) and b_(n) are thein-phase and quadrature phase amplitude coefficients respectively, andh(t−nT) is a channel impulse response function, which is a function oftime (t) and an index (n) times the timestamp (T) at which the signal istransmitted. In a general sense, a channel impulse response is areaction of a dynamic system in response to some external change, withthe impulse response describing the reaction as a function of time (oranother independent variable that parameterizes the dynamic behavior ofthe system). In typical DCRs, the incoming signal is passed through anI-channel mixer, configured to remove the in-phase frequency, and aQ-channel mixer, configured to remove the quadrature phase frequencythrough heterodyning. The I and Q channels are necessary for anglemodulated signals because the two channels contain different informationand may result in irreversible corruption if they overlap each otherwithout being separated into two phases. In typical DCRs, the signals inthe two channels are passed through respective LPFs, and added at theoutputs to obtain the demodulated signal.

In general, a frequency mixer is a 3-port electronic circuit, with twoinput ports (e.g., providing the incoming signal, and a referencesignal), and an output port. The ideal frequency mixer mixes theincoming signal and the reference signal from a local oscillator (LO)such that the output signal frequency (f_(out)) is either the sum (ordifference) of the frequencies (f_(in1), f_(in2)) of the inputs. Inother words:f _(out) =f _(in1) ±f _(in2)  (2)When the desired output frequency is lower than the frequency of theincoming signal, the process is called downconversion, and the outputfrequency is the difference of the frequencies of the two inputs. Whenf_(in1)=f_(in2), the output frequency is zero. The reference signal maybe either a sinusoidal continuous wave, or a square wave, depending onthe application. Any nonlinear device, such as Schottky diodes, galliumarsenide field effect transistors and complementary metal-oxidesemiconductor transistors can be used to make a mixer circuit.

Heterodyning is a radio signal processing technique, in which newfrequencies are created by combining or mixing two frequencies.Heterodyning is useful for frequency shifting signals into a newfrequency range, and is also involved in the processes of modulation anddemodulation. The two frequencies are combined in the mixer.Heterodyning is based on the trigonometric identity:sin θ sin φ=½ cos(θ−φ)−½ cos(θ+φ)  (3)The product sin θ sin φ represents the mixing of a sine wave withanother sine wave (e.g., in a mixer). The right hand side shows that theresulting signal is the difference of two sinusoidal terms, one at thesum of the two original frequencies, and the other at the difference ofthe two original frequencies, each of which can be considered to be aseparate signal.

In DCR applications, the incoming signal, having a frequency of ω_(c)may be mixed with a reference signal having the same frequency, creatingtwo output signals, one output signal having a frequency of 2ω_(c) andthe other output signal being a direct current (DC) component (havingzero frequency). Typically only one of the new frequencies (e.g., DCcomponent) is desired, and the other output signal is filtered out ofthe output of the mixer using the LPF.

In general, an LPF is an electronic filter that passes low-frequencysignals and attenuates signals with frequencies higher than a cutofffrequency. An ideal low-pass filter completely eliminates allfrequencies above the cutoff frequency while passing those belowunchanged (e.g., its frequency response can be considered to be arectangular function). Real filters for real-time applicationsapproximate the ideal filter by truncating the impulse response;however, the truncating can require delaying the signal for a moderateperiod of time. This delay can be manifested as a phase difference. TheLPFs can be mathematically represented by their respective tap weights,or filter coefficients (e.g., h_(a)[i]). An N-th order filter can berepresented by the taps h_(a)[0], h_(a)[1], . . . h_(a)[N−1].

Typically, the DCR acquires a complex signal, which is a distortedversion of a desired baseband signal. The distortions caused by thereceiver can be a result of the local oscillator phase error, which isfrequency independent and of the order of 2 to 3 degrees. To operatewithout I/Q errors, the local oscillator of the frequency mixer mustproduce signals with a phase shift of exactly 90°, which is impossibleto meet in practice. Moreover, the gains and phases responses of theI-channel and the Q-channel must be matched. However, in practice,mismatches in analog components cause an imbalance in the gain and phaseresponses of the I-channel and the Q-channel. The errors in thefrequency mixers can be denoted by a cumulative error in the I-channelmixer as a reference signal R:R=λ ₁ cos(ω_(c) t+λ ₂)  (4)where λ₁ represents the gain mismatch between the I-channel and theQ-channel, and λ₂ represents the phase mismatch of the local oscillator.(In the ideal scenario, λ₁=1, and λ₂=0.)

The distortions at the DCR can also be a result of a frequency dependentchannel impulse response mismatch between the LPFs in the I-channel andQ-channel. The LPFs in the I-channel and the Q-channel of the DCR musthave identical characteristics (e.g., identical tap weights). However,actual LPFs have slightly mismatched tap weights, which can lead to I/Qerrors, with different channel impulse response characteristics (i.e.,the channel impulse response mismatch) between the signals in theI-channel and the Q-channel. The errors from the phase differencebetween the oscillators of the frequency mixers and changes in the phasedifference between the LPFs in the I/Q paths can corrupt the signal to alarge extent and severely distort the signal to noise ratio. In general,the gain imbalance appears as a non-unity scale factor in the amplitudewhile the phase imbalance corrupts one channel with a fraction of datapulses in the other channel.

Turning to FIG. 1, FIG. 1 is a simplified block diagram of electricalcircuit 10 that implements circuit architecture for I/Q mismatchmitigation in direct conversion receivers. Electrical circuit 10 isconfigured to minimize I/Q mismatch based on injection of localoscillator phase error. According to various embodiments, incomingsignal 12 may be mathematically represented as s (provided earlierherein in equation (1)). An I-channel mixer 14 may approximatelytranslate an I-channel component of the incoming signal 12 to directcurrent (DC) by injecting a reference signal R as provided in equation(3) by a local oscillator (LO) 15. A Q-channel mixer 16 mayapproximately translate the Q-channel component of incoming signal 12 todirect current by injecting, by LO 15, another reference signal with aphase shift of 90° with the reference signal provided to I-channel mixer14.

A correlation adder 18 may add the output signals from I-channel mixer14 and Q-channel mixer 16 in an analog domain (e.g., signal processingspace in which signals representing physical measurements arecontinuous, and continuously varying). LPF 20 having filter coefficients{h_(α)[0], h_(α)[1], . . . h_(α)[N−1]} may remove high frequencies fromthe output signal of correlation adder 18, and output signal X 22.Signal X 22 may be passed through a correcting filter 24 (c1), and anoutput signal A 26 may be obtained therefrom.

The output signal from Q-channel mixer 16 may also be passed throughanother LPF 28 having filter coefficients {h_(β)[0], h_(β)[1], . . .h_(β)[N−1]}, which may remove the non-DC components from the signal, andoutput signal Y 30. Signal Y 30 may be passed through a correctingfilter 32 (c2) to obtain an output signal B 34. Correcting filters 24and 32 may be configured to remove mismatches between filtercoefficients of LPF 20 and LPF 28. For example, assume that LPF 20, LPF28, correcting filter 24 and correcting filter 32 are 3rd order filters,with the following filter coefficients: LPF 20 has the filtercoefficients {h_(α)[0], h_(α)[1], h_(α)[2]}; LPF 28 has the filtercoefficients {h_(β)[0], h_(β)[1], h_(β) [2]}; correcting filter 24 hasthe filter coefficients {c ₁[0], c₁[1], c₁[2]}; and correcting filter 32has the filter coefficients {c₂[0], c₂[1], c₂[2]}. Note that the filtercoefficients of LPF 20 and LPF 28 are known quantities, and the filtercoefficients of correcting filters 24 and 32 may be determined fromadditional computations. Assume, without loss of generality, thatc₂[0]=1. The filters can be mathematically represented by the followingequations:h _(α) =[h _(α)[0],h _(α)[1],h _(α)[2]]^(T)  (5)h _(β) =[h _(β)[0],h _(β)[1],h _(β)[2]]^(T)  (6)c ₁ =[c ₁[0],c ₁[1],c ₁[2]]^(T)  (7)c ₂=[1,c ₂[1],c ₂[2]]^(T)  (8)

Correcting filters 24 and 32 may be configured so thatr₁=h_(α)×c₁=r₂=h_(β)×c₂, where r₁ and r₂ are equivalent filtercoefficient matrices (e.g., set of equivalent filter coefficients)representing the combination of LPF 20 and correcting filter 24 in theI-channel, and LPF 28 and correcting filter 32 in the Q-channel,respectively. Filters having equivalent filter coefficients r₁ and r₂may represent low pass filters in the I-channel and the Q-channel,respectively, having identical tap weights, with no mismatches. Toremove the mismatch between the low pass filtering on the I-channel andthe Q-channel, r₁ may be equalized to r₂. Thus, the effective filteringbehavior of the I-channel and the Q-channel may be configured to beidentical. Mathematically, the matrix equation can be written in thefollowing form:

$\begin{matrix}{{\begin{bmatrix}{h_{1}\lbrack 0\rbrack} & 0 & 0 & 0 & 0 \\{h_{1}\lbrack 1\rbrack} & {h_{1}\lbrack 0\rbrack} & 0 & {- {h_{2}\lbrack 0\rbrack}} & 0 \\{h_{1}\lbrack 2\rbrack} & {h_{1}\lbrack 1\rbrack} & {h_{1}\lbrack 0\rbrack} & {- {h_{2}\lbrack 1\rbrack}} & {- {h_{2}\lbrack 0\rbrack}} \\0 & {h_{1}\lbrack 2\rbrack} & {h_{1}\lbrack 1\rbrack} & {- {h_{2}\lbrack 2\rbrack}} & {- {h_{2}\lbrack 1\rbrack}} \\0 & 0 & {h_{1}\lbrack 2\rbrack} & 0 & {- {h_{2}\lbrack 2\rbrack}}\end{bmatrix}\begin{bmatrix}{c_{1}\lbrack 0\rbrack} \\{c_{1}\lbrack 1\rbrack} \\{c_{1}\lbrack 2\rbrack} \\{c_{2}\lbrack 1\rbrack} \\{c_{2}\lbrack 2\rbrack}\end{bmatrix}} = \begin{bmatrix}{h_{2}\lbrack 0\rbrack} \\{h_{2}\lbrack 1\rbrack} \\{h_{2}\lbrack 2\rbrack} \\0 \\0\end{bmatrix}} & (9)\end{matrix}$Solving the matrix equation can lead to determining the correctingfilter coefficients {c₁[0], c₁[1], c₁[2]} and {c₂[0], c₂[1], c₂[2]}(with c₂[0]=1), and designing correcting filters 24 and 32 appropriately(e.g., with electrical components (e.g., resistors, capacitors, etc.)).

Alternatively, to create effective filters having the same equivalentfilter coefficients for the I-channel and the Q-channel, a predeterminedcost function may be minimized (e.g., to zero). The cost function mayproportional to a sum of squares of a difference between a first set ofequivalent filter coefficients {r₁[0], r₁[1], . . . r₁[N−1]} and asecond set of equivalent filter coefficients {r₂[0], r₂[1], . . .r₁[N−1]}:ƒ(r ₁ ,r ₂)=θ{(r ₁[0]−r ₂[0])²+(r ₁[1]−r ₂[1])²+ . . . +(r ₁ [N−1]−r ₂[N−1])²}  (10)where the first set of equivalent filter coefficients correspond to theI-channel signal component, and the second set of equivalent filtercoefficients correspond to the Q-channel signal component. The equationmay be re-written as:

$\begin{matrix}{{f\left( {r_{1},r_{2}} \right)} = {\theta\left\{ {{\sum\limits_{k = 0}^{N - 1}{r_{1}^{2}\lbrack k\rbrack}} + {\sum\limits_{k = 0}^{N - 1}{r_{2}^{2}\lbrack k\rbrack}} - {2{\sum\limits_{k = 0}^{N - 1}{{r_{1}\lbrack k\rbrack}{r_{2}\lbrack k\rbrack}}}}} \right\}}} & (11)\end{matrix}$If r₁=r₂ (as is the case with zero mismatch low pass filters in theI-channel and the Q-channel), the cost function ƒ(r₁,r₂) will be zero.The cost function can also be obtained by solving the followingequations:

$\begin{matrix}{{E\left\{ A^{2} \right\}} = {{{\sigma^{2}{\sum\limits_{k = 0}^{N - 1}{r_{1}^{2}\lbrack k\rbrack}}} + {\sigma^{2}{\sum\limits_{k = 0}^{N - 1}{r_{1}^{2}\lbrack k\rbrack}}}} = {2\sigma^{2}{\sum\limits_{k = 0}^{N - 1}{r_{1}^{2}\lbrack k\rbrack}}}}} & (12) \\{{E\left\{ B^{2} \right\}} = {\sigma^{2}{\sum\limits_{k = 0}^{N - 1}{r_{2}^{2}\lbrack k\rbrack}}}} & (13) \\{{E\left\{ {AB} \right\}} = {\sigma^{2}{\sum\limits_{k = 0}^{N - 1}{{r_{1}\lbrack k\rbrack}{r_{2}\lbrack k\rbrack}}}}} & (14) \\\begin{matrix}{{f\left( {r_{1},r_{2}} \right)} = {\frac{E\left\{ A^{2} \right\}}{2} + {E\left\{ B^{2} \right\}} - {2E\left\{ {AB} \right\}}}} \\{= {\sigma^{2}\left\{ {{\sum\limits_{k = 0}^{N - 1}{r_{1}^{2}\lbrack k\rbrack}} + {\sum\limits_{k = 0}^{N - 1}{r_{2}^{2}\lbrack k\rbrack}} - {2{\sum\limits_{k = 0}^{N - 1}{{r_{1}\lbrack k\rbrack}{r_{2}\lbrack k\rbrack}}}}} \right\}}}\end{matrix} & (15)\end{matrix}$where E{A} is the expected value of signal A 26, E{B} is the expectedvalue of signal B 34, and σ² is the power of incoming signal 12. Thus,the predetermined cost function may be a function of the power ofincoming signal 12.

The phase and gain imbalance between the I-channel and Q-channel may berepresented mathematically in matrix form as follows:

$\begin{matrix}{\begin{bmatrix}I \\Q\end{bmatrix} = {{\begin{bmatrix}\gamma_{1} & \gamma_{2} \\0 & {1/2}\end{bmatrix}\begin{bmatrix}{\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}}} \\{\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}}}\end{bmatrix}}\begin{bmatrix}h_{a} \\h_{a}\end{bmatrix}}} & (16)\end{matrix}$where γ₁ and γ₂ are errors in the phase and gain resulting fromnon-idealities in the DCR, and h_(a) is the filter coefficient of anidealized low pass filter on both I-channel and Q-channel. Multiplyingequation 12 by the inverse of the error matrix can remove the phase andgain error.

Signal A 26 may be mathematically represented as follows:

$\begin{matrix}{A = {\left\{ r_{1} \right\}\left\langle {\left\lbrack {{\left\{ {\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}}} \right\}{\cos\left( {\omega_{c}t} \right)}} + {\left\{ {\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}}} \right\}{\sin\left( {\omega_{c}t} \right)}}} \right\rbrack\left. \quad\left\lbrack {{\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right){\cos\left( {\omega_{c}t} \right)}} + {\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right){\sin\left( {\omega_{c}t} \right)}}} \right\rbrack \right\rangle} \right.}} & (17)\end{matrix}$Rearranging the terms, and rewriting A in terms of the effective filtercoefficients of the filter combination of LPF 20 and correcting filter24 (r₃×h=r₂×h=r₁×h):

$\begin{matrix}{A = {{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right){\sum\limits_{n}{a_{n}{r_{3}\left( {t - {nT}} \right)}}}} + {0.5\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right){\sum\limits_{n}{b_{n}{r_{3}\left( {t - {nT}} \right)}}}}}} & (18)\end{matrix}$If it is assumed that after filter calibration of LPFs 20 and 28 withcorrecting filters 24 and 32, there is no mismatch between the I-channeland Q-channel components, then, inserting a gain of

$\frac{1}{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}$to signal A 26 (e.g., at correcting filter 24) may yield a signal Ã asfollows:

$\begin{matrix}{\overset{\sim}{A} = {{A\left( \frac{1}{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)} \right)} = {{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right){\sum\limits_{n}{a_{n}\frac{1}{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}{r_{3}\left( {t - {nT}} \right)}}}} + {0.5\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right){\sum\limits_{n}{b_{n}\frac{1}{0.5\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}{r_{3}\left( {t - {nT}} \right)}}}}}}} & (19)\end{matrix}$The component

$\frac{\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right)}{\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}{\sum\limits_{n}{b_{n}{r_{3}\left( {t - {nT}} \right)}}}$may be canceled by multiplying the Q-channel signal component by

$\frac{\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right)}{\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}$and subtracting it from Ã. A scalar compensation coefficient, alpha 36,also called the “gain correction” may be defined as follows:

$\begin{matrix}{{Alpha} = \frac{\left( {1 - {\lambda_{1}{\sin\left( \lambda_{2} \right)}}} \right)}{\left( {\lambda_{1}{\cos\left( \lambda_{2} \right)}} \right)}} & (20)\end{matrix}$Gain correction alpha 36 may be a function of the gain mismatch (λ₁)between the outputs of I-mixer 14 in the I-channel and Q-mixer 16 in theQ-channel of electrical circuit 10, and the phase mismatch (λ₂) of LO15.

According to various embodiments, gain correction alpha 36, may be mixedwith output of correcting filter 32 at alpha mixer 38, and added (insome embodiments with a negative sign) with an output of correctingfilter 24 at gain correction adder 40, resulting in signal C 44 on theI-channel, and signal D 46 on the Q channel. Mathematically, in scalarform, signal C 44 and signal D 48 can be represented by the followingequations, respectively:

$\begin{matrix}{C = \left\lbrack {\sum\limits_{n}{a_{n}{r_{3}\left( {t - {nT}} \right)}}} \right\rbrack} & (21) \\{D = \left\lbrack {\sum\limits_{n}{b_{n}{r_{3}\left( {t - {nT}} \right)}}} \right\rbrack} & (22)\end{matrix}$where C is signal C 44, D is signal D 46, and r₃=r₂=r₁, the filtercoefficients of the calibrated filters obtained by combining LPF 20 andLPF 28 with correcting filters 24 and 32, respectively.

Turning to FIG. 2, FIG. 2 is a simplified block diagram illustratinganother embodiment of electrical circuit 10. Incoming signal 12 may bemathematically represented as s (provided earlier herein). An I-channelmixer 50 may be provided with a reference input signal R_(I) from LO 51as follows:R _(I)=λ₁ sin(ω_(c) t+λ ₂+θ)  (23)where θ is a predetermined phase shift with another reference signalprovided at Q-channel mixer 16. A compensation mixer 52 may multiply theoutput of I-channel mixer 50 with the constant factor, namely, one oversin(θ) (i.e., 1/sin(θ)), to compensate for the predetermined phase shiftθ added into the reference signal of I-channel mixer 50.

In some embodiments, θ may comprise 45°, and the constant factor mayequal two over square root of two (2/sqrt(2)). Adding 45° to thereference signal of I-channel mixer 14 and mixing with 2/sqrt(2) atcompensation mixer 52 may emulate adding the output of Q-channel mixer16 to the output of I-channel mixer 14 (with a reference signal having a90° phase shift from that at Q-channel mixer 16) using correlation adder18 of FIG. 1. Adding the output of Q-channel mixer 16 to the output ofI-channel mixer 14 in the analog domain may be complicated and prone toadditional errors. By emulating the addition using compensation mixer52, the circuit may be simplified without substantially impacting theperformance.

LPF 20 having filter coefficients {h_(α)[0], h_(α)[1], . . . h_(α)[N−1]}may remove DC components from the output of compensation mixer 52, andoutput signal X 22. Mathematically, signal X 22 may be represented asfollows:

$\begin{matrix}{X = {\left\{ h_{\alpha} \right\}\left\langle {\left\{ {{\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}{\cos\left( {\omega_{c}t} \right)}}} + {\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}{\sin\left( {\omega_{c}t} \right)}}}} \right\}{\sin\left( {{\omega_{c}t} + \theta} \right)}\frac{1}{\sin(\theta)}} \right\rangle}} & (24)\end{matrix}$Because sin(ω_(c)t+θ)=cos(ω_(c)t)sin(θ)+sin(ω_(c)t)cos(θ), X may berepresented as follows:

$\begin{matrix}{X = {\left\{ h_{\alpha} \right\}\left\langle {\left\{ {{\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}{\cos\left( {\omega_{c}t} \right)}}} + {\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}{\sin\left( {\omega_{c}t} \right)}}}} \right\}\left( {{\cos\left( {\omega_{c}t} \right)} + {{\sin\left( {\omega_{c}t} \right)}\left( \frac{\cos(\theta)}{\sin(\theta)} \right)}} \right)} \right\rangle}} & (25)\end{matrix}$Rearranging the terms yields the following equation for X:

$\begin{matrix}{X = {{\frac{1}{2}{\sum\limits_{n}{a_{n}{h_{1}\left( {t - {nT}} \right)}}}} + {\frac{1}{2}\frac{\cos(\theta)}{\sin(\theta)}{\sum\limits_{n}{b_{n}{h_{1}\left( {t - {nT}} \right)}}}}}} & (26)\end{matrix}$h₁=h_(α)×h, and sin²(ω_(c)t)=½ (1−cos(2ω_(c)t)); cos²(ω_(c)t)=½(1+cos(2ω_(c)t)); and sin(2ω_(c)t)=2 sin(ω_(c)t)cos(ω_(c)t). All theterms with 2ω_(c)t may be removed by LFP 20. In an example embodimentwhere θ is 45°,

$\frac{\cos\left( \frac{\pi}{4} \right)}{\sin\left( \frac{\pi}{4} \right)} = 1.$Thus, signal X 22 may be represented as follows:

$\begin{matrix}{X = {{\frac{1}{2}{\sum\limits_{n}{a_{n}{h_{1}\left( {t - {nT}} \right)}}}} + {\frac{1}{2}{\sum\limits_{n}{b_{n}{h_{1}\left( {t - {nT}} \right)}}}}}} & (27)\end{matrix}$It may be noted that as θ approaches 90°, the correlated term may beattenuated and the quality estimation may be poor. On the other hand, asθ approaches 0°, the gain at the I-channel may increase (e.g., toinfinity), indicating that the I-channel information may beover-attenuated, and therefore, the quality of estimation of theI-channel signal component may be poor. When θ approaches 45°, thequality estimation may reach an optimally desired value.

The output signal from Q-channel mixer 16 may also be passed throughanother LPF 28, which may remove the high frequency components from thesignal, and output signal Y 30. Signal Y 30 may be passed throughcorrecting filter 32 to obtain output signal B 34. Correcting filters 24and 32 may be configured to remove mismatches between filtercoefficients of LPF 20 and LPF 28.

According to various embodiments, gain correction alpha 36 (as describedearlier herein) may be mixed with signal B 34 at alpha mixer 38, andadded to the output of correcting filter 24, namely, signal A 26, atgain correction adder 40 to obtain signal C 44. Mathematically, signal A26 may be represented by the following matrix equation:

$\begin{matrix}{A = {\left\{ r_{1} \right\}\left\langle {\left\lbrack {{\left\{ {\sum\limits_{n}{a_{n}{h\left( {t - {nT}} \right)}}} \right\}{\cos\left( {\omega_{n}t} \right)}} + {\left\{ {\sum\limits_{n}{b_{n}{h\left( {t - {nT}} \right)}}} \right\}{\sin\left( {\omega_{c}t} \right)}}} \right\rbrack\left. \quad{\left\lbrack {{\lambda_{1}{\sin\left( {\lambda_{2} + \theta} \right)}{\cos\left( {\omega_{c}t} \right)}} + {\lambda_{1}{\cos\left( {\lambda_{2} + \theta} \right)}{\sin(\theta)}}} \right\rbrack\frac{1}{\sin(\theta)}} \right\rangle} \right.}} & (28)\end{matrix}$Because sin(λ₂+θ)=cos(λ₂)sin(θ)+sin(λ₂)cos(θ), A may be rewritten asfollows:

$\begin{matrix}{A = {{{0.5\left\lbrack {\lambda_{1}\left\{ {{\cos\left( \lambda_{2} \right)} + {\frac{\cos(\theta)}{\sin(\theta)}{\sin\left( \lambda_{2} \right)}}} \right\}} \right\rbrack}{\sum\limits_{n}{a_{n}{r_{3}\left( {t - {nT}} \right)}}}} + {0.5\left\{ {\lambda_{1}{\cos\left( {\lambda_{2} + \theta} \right)}} \right\}{\sum\limits_{n}{b_{n}{r_{3}\left( {t - {nT}} \right)}}}}}} & (29)\end{matrix}$By defining gain correction alpha 36 as a function of the gain mismatchλ₁ between the I-channel and Q-channel components, and λ₂, the phasemismatch of LO 15, for example,

${\alpha = \frac{\lambda_{1}{\cos\left( {\lambda_{2} + \theta} \right)}}{\lambda_{1}\left\{ {{\cos\left( \lambda_{2} \right)} + {\frac{\cos(\theta)}{\sin(\theta)}{\sin\left( \lambda_{2} \right)}}} \right\}}},$A can be rewritten in matrix form as:A=Xc ₁ +αYc ₂  (30)where A is the matrix form of signal A 26, X is the matrix form ofsignal X 22, Y is the matrix form of signal Y 30, α is gain correctionalpha 36 and c₁ and c₂ are the correcting filter coefficient matrices ofcorrecting filters 24 and 32, respectively. In scalar form, signal A 26may be represented as follows:

$\begin{matrix}{A = \left\lbrack {{\sum\limits_{n}{a_{n}{r_{1}\left( {t - {nT}} \right)}}} + {\sum\limits_{n}{b_{n}{r_{1}\left( {t - {nT}} \right)}}}} \right\rbrack} & (31)\end{matrix}$Signal B 44 may be mathematically represented by the following matrixequation:B=Yc ₂  (32)In scalar form, signal B 44 may be represented as follows:

$\begin{matrix}{B = \left\lbrack {\sum\limits_{n}{b_{n}{r_{2}\left( {t - {nT}} \right)}}} \right\rbrack} & (33)\end{matrix}$Gain correction alpha 36 may be obtained from minimizing the costfunction described earlier herein, by substituting for signal A andsignal B to obtain the cost function as follows:ƒ(r ₁ ,r ₂)=0.5a ^(T) X ^(T) Xa+0.5αb ^(T) Y ^(T) Yb+αa ^(T) X ^(T) Yb+b^(T) Y ^(T) Yb−2αb ^(T) Y ^(T) Yb−2αb ^(T) Y ^(T) Xa  (34)Rearranging the terms leads to the following equation for the costfunction:ƒ(r ₁ ,r ₂)=0.5c ₁ ^(T) X ^(T) Xc ₁ +c ₂ ^(T) Y ^(T) Yc ₂(1−1.5α)−αc ₂^(T) Y ^(T) Xc ₁  (35)

Because computations in the digital domain (e.g., signal processingspace where the signals are discrete time signals generated by digitalmodulation) are relatively easier than the same computations in theanalog domain, minimizing the predetermined cost function can beperformed in the digital domain to obtain the filter coefficients c₁ andc₂, and gain correction, alpha 36.

Turning to FIG. 3, FIG. 3 is a simplified block diagram illustratinganother example embodiment of electrical circuit 10. Incoming signal 12may be mathematically represented as s (provided earlier herein). AnI-channel mixer 50 may be provided with a reference input signal R_(I)from LO 51, as provided earlier herein. Reference signal R_(I) mayinclude a predetermined phase shift of θ(e.g., 45° in an exampleembodiment) with another reference signal provided at Q-channel mixer16. A compensation mixer 52 may multiply the output of I-channel mixer50 with the constant factor, namely, one over sin(θ) (e.g., two oversquare root of two (2/sqrt(2)) in an example embodiment where thepredetermined phase shift is 45°), to compensate for the predeterminedphase shift of θ added into the reference signal of I-channel mixer 50.LPF 20 may remove high frequency components from the output ofcompensation mixer 52.

According to some embodiments, an analog-to-digital converter (ADC) (notshown) may convert the analog output of LPF 20 to a digital signal. Theoutput signal from Q-channel mixer 16 may also be passed through LPF 28,which may remove the high frequency components from the signal.According to some embodiments, another ADC (not shown) may convert theanalog output of LPF 28 to a digital signal. The outputs from LPF 20 andLPF 28 may be provided to correcting filters 24 and 32, respectively. Inother embodiments, LPF 20 may include a digital filter that samples theoutput from compensation mixer 52 in the digital domain, and output adigital signal directly to DSP 58. Similarly, LPF 28 may include adigital filter that samples the output from Q-channel mixer 16 in thedigital domain, and output a digital signal.

A digital signal processor (DSP) 58 may listen to the outputs from LPF20 and LPF 28. DSP 58 may process the predetermined cost function toprovide appropriate gain correction alpha values and filter coefficientsc₁ and c₂ to correcting filters 24 and 32. DSP 58 may provide (and/orupdate) gain correction alpha 36 to alpha mixer 38. Correcting filters24 and 32 may correct the incoming I-channel signal component samplesand Q-channel signal component samples in real time while DSP 58 mayupdate the gain correction alpha values and filter coefficients c₁ andc₂ in real time as best effort. According to some embodiments, the besteffort operations can reduce power consumption of DSP 58. The outputfrom correcting filter 32, namely, signal B 34 may be mixed with alpha26 at alpha mixer 38 and added with the output from correcting filter24, namely, signal A 26 at gain correction adder 40. The output fromelectrical circuit 10 may comprise signal C 44 in the I-channel, andsignal D 46 in the Q-channel.

Note that in this Specification, references to various features (e.g.,elements, structures, modules, components, steps, operations,characteristics, etc.) included in “one embodiment”, “exampleembodiment”, “an embodiment”, “another embodiment”, “some embodiments”,“various embodiments”, “other embodiments”, “alternative embodiment”,and the like are intended to mean that any such features are included inone or more embodiments of the present disclosure, but may or may notnecessarily be combined in the same embodiments.

In one example embodiment, electrical circuit 10 of the FIGURES may beimplemented on a motherboard of an associated electronic device. Themotherboard can be a general circuit board that can hold variouscomponents of the internal electronic system of the electronic deviceand, further, provide connectors for other peripherals. Morespecifically, the motherboard can provide the electrical connections bywhich the other components of the system can communicate electrically.Any suitable processors (inclusive of digital signal processors,microprocessors, supporting chipsets, etc.), memory elements, etc. canbe suitably coupled to the motherboard based on particular configurationneeds, processing demands, computer designs, etc. Other components suchas external storage, additional sensors, controllers for audio/videodisplay, and peripheral devices may be attached to the motherboard asplug-in cards, via cables, or integrated into the motherboard itself.

In another example embodiment, electrical circuit 10 of the FIGURES maybe implemented as stand-alone modules (e.g., a device with associatedcomponents and circuitry configured to perform a specific application orfunction) or implemented as plug-in modules into application specifichardware of electronic devices. Note that particular embodiments of thepresent disclosure may be readily included in a system on chip (SOC)package, either in part, or in whole. An SOC represents an IC thatintegrates components of a computer or other electronic system into asingle chip. It may contain digital, analog, mixed-signal, and oftenradio frequency functions: all of which may be provided on a single chipsubstrate. Other embodiments may include a multi-chip-module (MCM), witha plurality of separate ICs located within a single electronic packageand configured to interact closely with each other through theelectronic package. In various other embodiments, the amplificationfunctionalities may be implemented in one or more silicon cores inApplication Specific Integrated Circuits (ASICs), Field ProgrammableGate Arrays (FPGAs), and other semiconductor chips.

It is also imperative to note that all of the specifications,dimensions, and relationships outlined herein (e.g., the number ofprocessors and memory elements, logic operations, etc.) have only beenoffered for purposes of example and teaching only. Such information maybe varied considerably without departing from the spirit of the presentdisclosure, or the scope of the appended claims. The specificationsapply only to one non-limiting example and, accordingly, they should beconstrued as such. In the foregoing description, example embodimentshave been described with reference to particular processor and/orcomponent arrangements. Various modifications and changes may be made tosuch embodiments without departing from the scope of the appendedclaims. The description and drawings are, accordingly, to be regarded inan illustrative rather than in a restrictive sense.

Note that with the numerous examples provided herein, interaction may bedescribed in terms of two, three, four, or more electrical components.However, this has been done for purposes of clarity and example only. Itshould be appreciated that the system can be consolidated in anysuitable manner. Along similar design alternatives, any of theillustrated components, modules, and elements of the FIGURES may becombined in various possible configurations, all of which are clearlywithin the broad scope of this Specification. In certain cases, it maybe easier to describe one or more of the functionalities of a given setof flows by only referencing a limited number of electrical elements. Itshould be appreciated that electrical circuit 10 of the FIGURES and itsteachings are readily scalable and can accommodate a large number ofcomponents, as well as more complicated/sophisticated arrangements andconfigurations. Accordingly, the examples provided should not limit thescope or inhibit the broad teachings of electrical circuit 10 aspotentially applied to a myriad of other architectures.

Numerous other changes, substitutions, variations, alterations, andmodifications may be ascertained to one skilled in the art and it isintended that the present disclosure encompass all such changes,substitutions, variations, alterations, and modifications as fallingwithin the scope of the appended claims. In order to assist the UnitedStates Patent and Trademark Office (USPTO) and, additionally, anyreaders of any patent issued on this application in interpreting theclaims appended hereto, Applicant wishes to note that the Applicant: (a)does not intend any of the appended claims to invoke paragraph six (6)of 35 U.S.C. section 112 as it exists on the date of the filing hereofunless the words “means for” or “step for” are specifically used in theparticular claims; and (b) does not intend, by any statement in thespecification, to limit this disclosure in any way that is not otherwisereflected in the appended claims.

What is claimed is:
 1. An electrical circuit, comprising: a localoscillator configured to generate a first reference signal and a secondreference signal having a predetermined phase shift with the firstreference signal; an I-channel mixer configured to inject the firstreference signal to an incoming signal and generate a first output,wherein the incoming signal includes an I-channel signal component and aQ-channel signal component; a compensation mixer configured to multiplythe first output with a constant factor to generate a second output,wherein the second output includes the I-channel signal component andthe Q-channel signal component; a first low pass filter configured toattenuate frequencies in the second output to generate a third output;and a first correcting filter configured to filter the third output togenerate a fourth output, wherein the first correcting filter isconfigured to reduce a channel impulse response mismatch between thefirst low pass filter and a second low pass filter, wherein the secondlow pass filter is configured to attenuate frequencies in a Q-channel ofthe incoming signal.
 2. The electrical circuit of claim 1, wherein thefirst reference signal and the second reference signal comprisesinusoidal functions.
 3. The electrical circuit of claim 1, wherein theconstant factor is equal to one over sine of the phase shift.
 4. Theelectrical circuit of claim 1, wherein the phase shift comprises 45° andthe constant factor is equal to two over square root of two.
 5. Theelectrical circuit of claim 1, wherein the I-channel mixer and thecompensation mixer are in an analog domain, and wherein the first lowpass filter and the first correcting filter are in a digital domain. 6.The electrical circuit of claim 5, further comprising: a Q-channel mixerconfigured to inject the second reference signal to the incoming signalto generate a fifth output, wherein the second low pass filter isconfigured to attenuate frequencies in the fifth output to generate asixth output; a second correcting filter configured to filter the sixthoutput to generate a seventh output, wherein the second correctingfilter is configured to reduce the channel impulse response mismatchbetween the first low pass filter and the second low pass filter; analpha mixer configured to inject a gain correction to the seventh outputto generate an eighth output; and a gain correction adder configured toadd the eighth output with the fourth output to generate a ninth output.7. The electrical circuit of claim 6, wherein the gain correctioncomprises a function of a gain mismatch between the first output and thefifth output, and a phase mismatch of the local oscillator.
 8. Theelectrical circuit of claim 6, wherein the Q-channel mixer is in ananalog domain and wherein the second low pass filter, the secondcorrecting filter, the alpha mixer, and the gain correction adder are ina digital domain.
 9. The electrical circuit of claim 6, wherein a firstset of filter coefficients of the first correcting filter, a second setof filter coefficients of the second correcting filter and the gaincorrection are determined by minimizing a predetermined cost function.10. The electrical circuit of claim 9, wherein the cost function isproportional to a sum of squares of a difference between a first set ofequivalent filter coefficients and a second set of equivalent filtercoefficients, wherein the first set of equivalent filter coefficientscorrespond to the I-channel signal component, and the second set ofequivalent filter coefficients correspond to the Q-channel signalcomponent.
 11. The electrical circuit of claim 9, wherein the costfunction varies with a power of the incoming signal.
 12. The electricalcircuit of claim 9, wherein the cost function is processed by a digitalsignal processor.
 13. The electrical circuit of claim 12, wherein thedigital signal processor inserts the first set of filter coefficientsinto the first correcting filter, the second set of filter coefficientsinto the second correcting filter and the gain correction into the alphamixer.
 14. An electrical circuit, comprising: a local oscillatorconfigured to generate a first reference signal and a second referencesignal having a predetermined phase shift with the first referencesignal; an I-channel mixer configured to inject the first referencesignal to an incoming signal and generate a first output; a Q-channelmixer configured to inject the second reference signal to the incomingsignal to generate a second output; a correlation adder configured toadd the first output with the second output and generate a third output;a first low pass filter configured to attenuate frequencies in the thirdoutput to generate a fourth output; a first correcting filter configuredto filter the fourth output to generate a fifth output; a second lowpass filter configured to attenuate frequencies in the second output togenerate a sixth output; and a second correcting filter configured tofilter the sixth output to generate a seventh output, wherein the firstcorrecting filter and the second correcting filter are configured toreduce a channel impulse response mismatch between the first low passfilter and the second low pass filter.
 15. The electrical circuit ofclaim 14, wherein the phase shift comprises 90°.
 16. The electricalcircuit of claim 14, further comprising: an alpha mixer configured toinject a gain correction to the seventh output to generate an eighthoutput; and a gain correction adder configured to add the eighth outputwith the fifth output to generate a ninth output.
 17. The electricalcircuit of claim 16, wherein the I-channel mixer, the Q-channel mixerand the correlation adder are in an analog domain, and wherein the firstlow pass filter, the first correcting filter, the second low passfilter, the second correcting filter, the alpha mixer, and the gaincorrection adder are in a digital domain.
 18. The electrical circuit ofclaim 16, wherein a first set of filter coefficients of the firstcorrecting filter, a second set of filter coefficients of the secondcorrecting filter and the gain correction are determined by minimizing apredetermined cost function.
 19. The electrical circuit of claim 18,wherein the cost function varies with a power of the incoming signal.